Antenna-less rfid tag

ABSTRACT

A semi-passive radio frequency identification (RFID) tag includes a digital circuit with switching components operating within an interrogation range of an incident carrier wave. A plurality of input connections and output connections direct data communications through the switching components within the digital circuit, and the data communications are subject to switching operations of the switching components between at least one of the input connections and at least one of the output connections. A backscatter response reflected from the digital circuit upon arrival of the incident carrier wave, wherein the backscatter response is a modulated backscatter response in the presence of the switching operations.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and incorporates by references U.S.Provisional Patent Application Ser. No. 62/768,335 filed on Nov. 16,2019 and titled Antenna-less RFID Tag.

GOVERNMENT SUPPORT CLAUSE

This invention was made with government support under Grant No. 1651273and Grant No. 1740962 awarded by the National Science Foundation andGrant No. N00014-17-1-2540 awarded by the Office of Naval Research. Thegovernment has certain rights in the invention.

BACKGROUND

Radio-frequency identification (RFID) and near-field communication (NFC)have been widely used in everyday life. Radio-frequency identificationis typically used in supply chain management, asset tracking, dataexchange, telemetry, access control, etc. [1]-[9] and has a market thatis worth several billion dollars today and is expected to grow more than10% per year [10]. On the other hand, near-field communication (NFC),also referred to as inductive-coupled RFID, is extensively used forpromotional marketing, smart posters, security, files exchange,contactless payment, etc. [11] and has market that is expected to reachUSD 47.43 billion by 2024 [12]. There are two main classes of RFID tags:chip-based, which use an integrated circuit (IC) chip to store taginformation [8], [13]-[15], and chip-less, which use the electromagneticsignature of the all-passive tag substrate to store the information[16]-[18]. The RFIDs can also be classified as passive, semi-passive,and active depending on whether the tag uses electromagnetic sources forpower and communication, uses battery power for only its IC circuits, oruses battery power for both IC circuits and communication. Existing RFIDtags with computational chips [20]-[22] can only transmit 1 bitsimultaneously. Existing analog-signal side-channels, such as EMemanations, are a consequence of current-flow changes that are dependenton activity inside electronic circuits. In this disclosure, a new classof side-channels is set forth that is a consequence of impedance changesin switching circuits, referred to herein as an impedance-basedside-channel. One motivation to explore impedance-based side-channelswas a hypothesis that the backscatter radio effect should be present inelectronic devices.

A description of traditional backscatter data communication is a usefulstarting point. Traditional backscattering communication in prior artFIG. 1A refers to a radio channel where a reader sends a continuouscarrier wave (CW) signal and retrieves information from a modulated wavescattered back from a tag. During backscatter operation, the inputimpedance of a tag antenna is intentionally mismatched by two-state RFloads (Z0 and Z1) to vary the tag's reflection coefficient and tomodulate the incoming CW [25], [26].

Therefore, what is needed is an RFID tag that is flexible, accurate, andcapable of achieving a high data rate.

SUMMARY

To improve the prediction accuracy and to overcome the limitation inspatial and temporal extensibility of individual empirical models,systems, methods and devices are disclosed.

In one embodiment, a semi-passive radio frequency identification (RFID)tag includes a digital circuit with switching components operatingwithin an interrogation range of an incident carrier wave. A pluralityof input connections and output connections direct data communicationsthrough the switching components within the digital circuit, and thedata communications are subject to switching operations of the switchingcomponents between at least one of the input connections and at leastone of the output connections. A backscatter response reflected from thedigital circuit upon arrival of the incident carrier wave, wherein thebackscatter response is a modulated backscatter response in the presenceof the switching operations.

It should be understood that the above-described subject matter may alsobe implemented as a computer-controlled apparatus, a computer process, acomputing system, or an article of manufacture, such as acomputer-readable storage medium. Other systems, methods, featuresand/or advantages will be or may become apparent to one with skill inthe art upon examination of the following drawings and detaileddescription. It is intended that all such additional systems, methods,features and/or advantages be included within this description and beprotected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments and together with thedescription, serve to explain the principles of the methods and systems:

FIG. 1A is a PRIOR ART representation of a known RFID tag identificationsystem.

FIG. 1B is a schematic representation of one example chip used as anRFID tag as set forth in this disclosure.

FIG. 2A is a PRIOR ART schematic representation of a digital circuitimplementing an output circuit of a CMOS-NAND gate as set forth in oneexample of this disclosure.

FIG. 2B is a schematic representation of a low voltage input at theCMOS-NAND gate of FIG. 2A, turning on a PMOS transistor therein, andyielding a high state resistance (R1) and a distinct radar cross sectionof a backscatter response at the PMOS transistor as set forth in oneexample of this disclosure.

FIG. 2C is a schematic representation of a high voltage input at theCMOS-NAND gate of FIG. 2A, turning on an NMOS transistor therein, andyielding a low state resistance (R0) upon the NMOS transistor thereinand a distinct radar cross section of a backscatter response as setforth in one example of this disclosure.

FIG. 3 is a diagram of a shift register utilizing a series of flip flopcircuit components as disclosed in one example herein.

FIG. 4A is a diagram of an FPGA internal structure as set forth in oneexample of this disclosure.

FIG. 4B is a PRIOR ART diagram of one programmable flip flop circuitcomponent used to implement a digital circuit as described in at leastone example of this disclosure.

FIG. 4C is a PRIOR ART diagram of an equivalent circuit of the CMOS-NANDgate of FIG. 2A.

FIG. 5 is an illustration of the relationship between the modulationperiod (1/f_(m)) and the clock period (f/f_(clock)) in a circuit offlip-flops switching in a switching signal pattern at f_(m)=900 kHz.

FIG. 6A is an illustration of a first logic utilization mapping of anexemplary FPGA chip as described herein.

FIG. 6B is an illustration of a second logic utilization mapping of anexemplary FPGA chip as described herein.

FIG. 6C is an illustration of a third logic utilization mapping of anexemplary FPGA chip as described herein.

FIG. 7 is a block diagram of a multi-bit RFID tag illustrating eachtransmitted bit in a respective information data channel as a modulatedbackscatter signal from a respective section of a digital circuit at arespective modulation frequency fm_(x) where x ranges from 1 to M′. FIG.7 illustrates building blocks of the multi-bit RFID tag. M′ is thenumber of total shift registers (bits). N_(M′) is the number of totalconfigured flip-flops in an example circuit where fm_(M′) is themodulating frequency of the M′th shift register.

FIG. 8 is an illustration of an experimental result, showing themeasured backscatter power at three different carrier frequencies andthe backscatter frequency when an FPGA board is turned on, but notswitching, and utilizing a low noise amplifier (GNA-130F) as appliedherein. The different traces show measured backscatter power withfcarrier=17.46 GHz and fm=900 kHz (green), 1.2 MHz (red), and 1.6 MHz(yellow), respectively. The standby curve (blue) is the measuredbackscatter signal when FPGA board is turned on but not switching.

FIG. 9 is a diagram of an exemplary CMOS driver circuit based on NMOSand PMOS transistor models as set forth in examples of this disclosure.

FIG. 10 is an illustration depicting the simulated on-resistance of anASIC's NMOS transistor with (W, L)=(0.48 um, 0.16 um) as VDD sweeps from0 V to 3 V.

FIG. 11 is an illustration depicting the simulated on-resistance of anASIC's PMOS transistor with (W, L)=(0.16 um, 0.16 um) as VDD sweeps from0 V to 3 V.

FIG. 12A is a depiction of a test configuration including an AlteraCyclone V FPGA board as used in examples of this disclosure.

FIG. 12B is a depiction of a test configuration for example measurementsetups for a carrier wave having a carrier frequency of 5.8 GHz.

FIG. 12C is a depiction of a test configuration for example measurementsetups for a carrier wave having a carrier frequency of 17.46 GHz.

FIG. 12D is a depiction of a test configuration for example measurementsetups for a carrier wave having a carrier frequency of 26.5 GHz.

FIG. 13 is an illustration of experimental results showing the measuredpower of a 1-bit RFID with 100% logic resources, measured at 2 meters,with a carrier frequency of 17.46 GHz and a modulation frequency of 900kHz.

FIG. 14 is an illustration of experimental results showing the measuredpower of a 6-bit static ID RFID with 16% of logic resources assigned toeach bit. The modulation frequency ranges from 860 kHz to 1.04 MHz.

FIG. 15 is an illustration of experimental results showing the measuredpower of a 5.8 GHz 12-bit static ID with 8% of logic resources assignedto each bit, with the modulation frequency ranging from 700 kHz to 1.04MHz.

FIG. 16 is an illustration of experimental results showing the measuredpower of a 6-bit static ID with 16% of logic resources assigned to eachbit, with the modulation frequency ranging from 860 kHz to 1.04 MHz.

FIG. 17 is an illustration of experimental results showing the measuredpower of a 12-bit static ID RFID with 8% of logic resources assigned toeach bit with the modulation frequency ranging from 700 kHz to 1.04 MHz.

FIG. 18 is an illustration of experimental results showing the measuredpower of a 36-bit static ID with 2.7% of logic resources assigned toeach bit with the modulation frequency ranging between 300 kHz to 1.04MHz.

FIG. 19 is an illustration of experimental results showing the measuredsignal of a 4-bit RFID configured for dynamic communications where themodulation frequency ranges from 1 MHz to 1.14 MHz.

FIG. 20 is an illustration of experimental results showing the measuredsignal of an 8-bit RFID configured for dynamic communications where themodulation frequency ranges from 1 MHz to 1.39 MHz.

FIG. 21 is an illustration of experimental results showing the measuredsignal of a 12-bit RFID configured for dynamic communications where themodulation frequency ranges from 1 MHz to 1.79 MHz.

FIG. 22 is an illustration of the measured signal strength of thetransmitted symbols depicting both the modulated backscatter signals andthe post-measurement signal processing sampled signals.

FIG. 23 illustrates an exemplary computer that may comprise all or aportion of an antenna-less RFID tag or an antenna-less RFID tag controlsystem, and/or a separate control system; conversely, any portion orportions of the computer illustrated in FIG. 23 may comprise all or aportion of an antenna-less RFID tag or an antenna-less RFID tag controlsystem.

DETAILED DESCRIPTION

Before the present methods and systems are disclosed and described, itis to be understood that the methods and systems are not limited tospecific synthetic methods, specific components, or to particularcompositions. It is also to be understood that the terminology usedherein is for the purpose of describing particular embodiments only andis not intended to be limiting.

As used in the specification and the appended claims, the singular forms“a,” “an” and “the” include plural referents unless the context clearlydictates otherwise. Ranges may be expressed herein as from “about” oneparticular value, and/or to “about” another particular value. When sucha range is expressed, another embodiment includes from the oneparticular value and/or to the other particular value. Similarly, whenvalues are expressed as approximations, by use of the antecedent“about,” it will be understood that the particular value forms anotherembodiment. It will be further understood that the endpoints of each ofthe ranges are significant both in relation to the other endpoint, andindependently of the other endpoint. “Optional” or “optionally” meansthat the subsequently described event or circumstance may or may notoccur, and that the description includes instances where said event orcircumstance occurs and instances where it does not.

Throughout the description and claims of this specification, the word“comprise” and variations of the word, such as “comprising” and“comprises,” means “including but not limited to,” and is not intendedto exclude, for example, other additives, components, integers or steps.“Exemplary” means “an example of” and is not intended to convey anindication of a preferred or ideal embodiment. “Such as” is not used ina restrictive sense, but for explanatory purposes.

Disclosed are components that can be used to perform the disclosedmethods and systems. These and other components are disclosed herein,and it is understood that when combinations, subsets, interactions,groups, etc. of these components are disclosed that while specificreference of each various individual and collective combinations andpermutation of these may not be explicitly disclosed, each isspecifically contemplated and described herein, for all methods andsystems. This applies to all aspects of this application including, butnot limited to, steps in disclosed methods. Thus, if there are a varietyof additional steps that can be performed it is understood that each ofthese additional steps can be performed with any specific embodiment orcombination of embodiments of the disclosed methods.

The present methods and systems may be understood more readily byreference to the following detailed description of preferred embodimentsand the Examples included therein and to the Figures and their previousand following description. As will be appreciated by one skilled in theart, the methods and systems may take the form of an entirely hardwareembodiment, an entirely software embodiment, or an embodiment combiningsoftware and hardware aspects. Furthermore, the methods and systems maytake the form of a computer program product on a computer-readablestorage medium having computer-readable program instructions (e.g.,computer software) embodied in the storage medium. More particularly,the present methods and systems may take the form of web-implementedcomputer software. Any suitable computer-readable storage medium may beutilized including hard disks, CD-ROMs, optical storage devices, ormagnetic storage devices.

Embodiments of the methods and systems are described below withreference to block diagrams and flowchart illustrations of methods,systems, apparatuses and computer program products. It will beunderstood that each block of the block diagrams and flowchartillustrations, and combinations of blocks in the block diagrams andflowchart illustrations, respectively, can be implemented by computerprogram instructions. These computer program instructions may be loadedonto a general-purpose computer, special purpose computer, or otherprogrammable data processing apparatus to produce a machine, such thatthe instructions which execute on the computer or other programmabledata processing apparatus create a means for implementing the functionsspecified in the flowchart block or blocks.

These computer program instructions may also be stored in acomputer-readable memory that can direct a computer or otherprogrammable data processing apparatus to function in a particularmanner, such that the instructions stored in the computer-readablememory produce an article of manufacture including computer-readableinstructions for implementing the function specified in the flowchartblock or blocks. The computer program instructions may also be loadedonto a computer or other programmable data processing apparatus to causea series of operational steps to be performed on the computer or otherprogrammable apparatus to produce a computer-implemented process suchthat the instructions that execute on the computer or other programmableapparatus provide steps for implementing the functions specified in theflowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrationssupport combinations of means for performing the specified functions,combinations of steps for performing the specified functions and programinstruction means for performing the specified functions. It will alsobe understood that each block of the block diagrams and flowchartillustrations, and combinations of blocks in the block diagrams andflowchart illustrations, can be implemented by special purposehardware-based computer systems that perform the specified functions orsteps, or combinations of special purpose hardware and computerinstructions.

This disclosure introduces a new class of side-channels that is aconsequence of impedance differences in switching circuits, and referredto herein as an impedance-based side-channel. In one non-limiting theoryof operation, impedance differences between transistor gates 200 in thehigh-state 282 and in the low-state 280 change the radar cross section(RCS) 288, 289 of the back-scatter response and modulate thebackscattered signal 287A, 287B. This theory of operation yields aproposed digital circuit that can be used as a semi-passive RFID tag.The RFID tag may be implemented in a field programmable gate array 499(FPGA) as one non-limiting proof of concept. Proposed tags can bedirectly used in state-of-the-art smartphones such as Apple iPhone 7 andSamsung Galaxy S5 [19] that already have an FPGA board as a replacementfor near-field communication (NFC) chips. More importantly, thisapproach opens up new possibilities for RFID designers to experimentwith impedances of transistors switching from high-state to low-stateand further optimize this transmission mechanism in ASIC designs. Thisdisclosure describes in depth investigations into the possibility ofimplementing a proposed RFID tag on an ASIC for backscatter signalenhancement. Simulation results show that a 30 dB enhancement can beachieved by optimizing logic gates' impedances.

To illustrate flexibility of this design (circuit can be easilyreprogrammed), one experiment interrogated the proposed RFID tag at thefollowing frequencies: 1) 5.8 GHz, a frequency typically used for RFIDcommunications, 2) 17.46 GHz, a frequency identified to have the highestsignal-to-noise ratio (SNR), and 3) 26.5 GHz, a frequency that can beused for 5G wireless communications. Additionally, this disclosureillustrates a variety of RFID applications to demonstrate flexiblebit-configuration structures. State-of-the-art RFID tags are selected tocompare to newly proposed RFID applications, which include: static IDswith 6, 12, and 36 bits, multi-bit (4, 8, and 12 bits) dynamic RFID tag,and single-bit dynamic RFID tag. The proposed static ID configurationscan transmit up to 36 bits simultaneously and provide up to 68.7 billion(236) combinations of unique IDs. The number and pattern of bits arefully re-configurable. This flexible bit design does not occupyadditional space on the printed circuit board of the FPGA as the numberof bits increases.

The proposed dynamic RFID tags with 4 bits, 8 bits, and 12 bits wereimplemented, and all bits were successfully detected. The achieved datarates are comparable with work in below noted reference [9], where both16-QAM (quadrature amplitude modulation) and 4-PSK (phase shift keying)RFIDs are designed. This disclosure shows that a single-bit dynamic RFIDtag has been tested as well. By transmitting one bit of information at atime to have better SNR, the proposed RFID tag can achieve a data rateof 100 kbits/sec with a bit error rate (BER) of 0.00000183 (10-6), whichis comparable to state-of-the-art RFIDs in references [23] and [24]. Therest of the disclosure includes full descriptions of exampleimplementations including, but not limited to, an impedance-basedside-channel used for creating a backscattering communicationinformation channel as illustrated in FIG. 7, Ref 730. FIG. 7illustrates how information channels 730 can transmit modulatedbackscatter data 727 that is discernible from the backscatter response.The disclosure further investigates the possibility of implementing theproposed RFID on ASIC, and describes digital circuit design for proposedRFID tag. Other portions of this disclosure describe measurement setupand tests to determine the maximum range at which the new tag can beoperated. This disclosure includes applications of the proposed RFID tagacross frequencies of 5.8 GHz, 17.46 GHz, and 26.5 GHz.

One non-limiting hypothesis for how circuits described herein mayprovide the above noted information channels 730 was that inverters 200in digital electronics also have two-state RF loads and can be designedto reflect the modulated signal 288, 289. For example, as shown in FIG.2, when input voltage is low, NMOS transistors 210, 215 in inverters areoff and PMOS transistors 200, 225 are on. A direct path 282 existsbetween Vout 250 and VDD 275, resulting in a high output state 280. Onthe other hand, high input results in a low output state. As shown inFIG. 2B there exists a finite resistance R1 between the output 250 andVDD 275 and between the output 250 and the ground 290, respectively.See, e.g., Ref. [27]. The switching between the example NAND logic'shigh output state (R1) and low output state (R0) creates impedancevariation in the example of FIG. 2, which is analogous to the variationin antenna terminating impedance in typical RFID tags of FIG. 1A. Theimpedance variation creates a difference in the circuit's radar crosssection (RCS) illustrated as a variable back scatter radiation field288, 289, and thus modulates the electronic backscatter signals. To testthis hypothesis, this disclosure uses a Field-Programmable Gate Array(FPGA) 499 and an example program of a cyclical shift register 300 outof flip-flops 305, 315, 325 shown in FIG. 3 that consists of a largenumber of inverters 400, 405, 410, 415 connected in parallel as shown inFIG. 4, where A, B, C, D designations illustrate sets of invertersoperating at a same modulation frequency. As shown in FIG. 3, a shiftregister 300 is a group of flip-flops 305, 315, 325 set up in a linearfashion with their inputs and outputs connected together such that thedata is shifted from one device to another when the circuit is active.FIG. 3 illustrates use of linear feedback shift registers (LFSRs), i.e.,the shift register 300 connects the most significant bit, MSB (FFN inFIG. 3) back to the least significant bit, LSB (FF1 in FIG. 3) to causethe function to endlessly cycle through a sequence of patterns.

A simplified internal structure of an FPGA chip is shown in FIG. 4Awhere logic blocks are arranged in a two-dimensional grid and areconnected by a programmable routing inter-connects. This symmetricalgrid is connected to I/O blocks 480 which make off-chip connections. The“programmable/re-configurable” term in FPGAs indicates their ability toimplement a new function on the chip after its fabrication is complete.Logic blocks can be simplified as programmable flip-flops 425 shown inFIG. 4B. Most flip flops are based on CMOS-NAND gates due to their lowlatency. An equivalent output circuit 450 of a CMOS-NAND gate is shownin prior art FIG. 4C. When input voltage is low, NMOS transistors areoff and PMOS transistors are on. A direct path exists between Vout andVDD, resulting in a high output state. On the other hand, high inputresults in a low output state. This change between states with differentimpedance creates a difference in the circuit's radar cross section(RCS) and thus modulates the electronic backscatter signals.

In order to modulate an incident carrier wave (CW) signal, thisdisclosure illustrates flip-flops programmed to switch in a patternshown in FIG. 5. Flip-flops continuously switch between high state andlow state at a clock frequency (fclock), such as but not limited to 50MHz for half of a cycle 515 and stay quiet for the other half the cycle518. The switching cycle (modulating frequency, fm) directly relates tothe modulated signal bandwidth, i.e., the first harmonic of themodulated backscatter signal will be located at fcarrier±fm. By changingfm, one can upshift or downshift the modulated signals, making designvery flexible. Note that fm should be selected to avoid undesiredharmonics in higher frequencies, i.e., the highest sideband (fm) needsto be less than three times of the lowest sideband (fm), and to complyradio regulations and avoid interference from other radio systems.Please note that in practice, the switching transistors do not produceideal square pulses but rather pulses that have rising edges 2200A andfalling edges 2200B shown in FIG. 22 for example, which sometimes leadto appearance of signals at even harmonics of the modulated backscattersignal. To avoid undesired interference, the highest sideband (fm)should be less than two times of the lowest sideband (fm).

Other digital units that have periodic behavior, such as voltageregulators, are also candidates for use in developing an antenna-lesstag and typically produce signals in frequency ranges much lower than aprocessor clock. One of the reasons for that is to minimize interferencebetween periodic activities that tend to produce multiple harmonics onthe board. When designing RFID, knowledge of frequencies of periodicactivities on the board will help determine where to positionfrequencies of RFID modulated sidebands. The potential interferingfrequencies caused by other digital units can be found using methodproposed in reference [28] noted below.

In addition to the switching pattern, the number ofsimultaneously-switched elements is another factor that affectselectronic backscattering modulation. The more flip-flops are switchingin unison, the stronger the backscatter signal is. To control the numberof elements that switch simultaneously, one example embodiment use anN-bit shift register shown in FIG. 3, where N can be used to control thenumber of simultaneously-toggled flip-flops. FIG. 3 shows a simplifiedschematic for a 3-bit shift register, created by connecting N=3flip-flops (FFs) 305, 315, 325. FIG. 6 shows how logic is mapped onto anAltera Cyclone V FPGA chip for different values of N. Dark blue blocksrepresent utilized resources (flip-flops and logic) while light blueblocks denote unused resources. This Cyclone V FPGA chip is completelyutilized (100% design in FIG. 6) when N=36600, and designs with 50% and30% utilization use N=18300 and N=10980, respectively. Note that otherFPGA chips may contain different numbers of programmable elements (totalavailable N), so the same utilization percentage may require differentvalues of N to be selected when using other FPGA chips.

The proposed RFID tag operates the same as traditional RFID when onlyone inverter is used to create two impedance states, i.e., only asingle-bit single-sideband transmission is created. However, when higherdata rate is needed, traditional RFID uses multiple amplitude and/orphase levels and multi-bit modulation schemes to transmit the message ina single-sideband transmission. With dedicated ASIC, the proposed RFIDcan be designed in a similar fashion. However, it is also possible tohave multiple inverters 400A-D, 405A-D, 410A-D, 415A-D in the FPGA 499that switch at different frequencies, allowing for dynamic or staticmulti-bit designs using frequency modulation as shown in FIG. 4. Theadvantage of multi-frequency design is that receiver design is muchsimpler. For example, it does not require channel equalization andsynchronization and detection is much simpler. To generate multiple bitsas demonstrated herein, multiple shift registers 700, 715, 725 in FIG. 7are used to switch at different fm. Parameter M′ represents the numberof total shift registers. Parameter N_(M′) denotes the number of totalconfigured flip-flops in the M^(′th) shift register. The more flip-flopsare configured for a given bit's information data channel 730A, 730B,730C, the higher SNR can be achieved. Parameter f_(mM′) is themodulating frequency of the M^(′th) shift register, which affects thelocation of each side band and corresponding bandwidth for thecommunications. FIG. 7 illustrates that a digital circuit 750 comprisingswitching components 700, 715, 725 operating within an interrogationrange of an incident carrier wave may include a plurality of inputconnections D and output connections Q directing data communicationsthrough the switching components within the digital circuit, wherein thedata communications are subject to switching operations of the switchingcomponents between at least one of the input connections and at leastone of the output connections. A backscatter response 727 is reflectedfrom the digital circuit upon arrival of an incident carrier wave (notshown), wherein the backscatter response is a modulated backscatterresponse in the presence of the switching operations.

Next, this disclosure demonstrates that backscattered sidebands, such asthose shown schematically at 727 in FIG. 7, are actually created bychanging a switching frequency of the FPGA circuits, such as those shownin FIG. 4. The switching frequencies of the flip-flops in the FPGA boardare varied from fm=900 kHz, to 1.2 MHz, and to 1.6 MHz with logicutilization of 100%. For one non-limiting example, measurement setup ispresented in FIG. 12C. A low noise amplifier, GNA-130F from RF Bay Inc.[29] is used and Pt is 15 dBm. FIG. 8 shows the measurement results withfm=900 kHz (circle), 1.2 MHz (six-pronged star), and 1.6 MHz (triangle).The standby curve (X) is the measured backscattered signal when FPGAboard is turned on but not switching. Distinct modulated sidebands areobserved at 17.46 GHz±900 kHz, 17.46 GHz±1.2 MHz, and 17.46 GHz±1.6 MHz.Signal strength of the modulated sidebands reaches up to −85 dBm, whichis sufficient for commercial-available RFID readers in references [30]and [31] with sensitivity of −120 dBm and −125 dBm to detect. Thisresult shows that our proposed RFID technology can be used forcommercial applications.

In the standby mode, other sidebands around 17.46 GHz are also observed.Since the measurement is conducted in an indoor office environment,these sidebands are results from surrounding interference, e.g.,measurement instruments, LCD monitors, mobile phones, WiFi routers, etc.Note that conductive traces, such as those shown in FIG. 4, on an FPGAboard that connect the FPGA chip 499 to GPIO pins may act as antennasand radiate the backscatter signal. We disconnect these traces to verifythat the signal is coming from the FPGA chip itself and not from theboard. When turned on, GPIO pins 480 can still operate correctly butwill produce stronger RFID signal. Experimental results in FIG. 8 verifythat switching electronics can establish backscattering channels withoutany antennas and RF front-end circuits.

The proposed tag does not have to be implemented in FPGA. Specializedcircuits, e.g., ASICs, can be fabricated and the impedance differencebetween NAND logic's high output and low output state can be furtheroptimized. This disclosure shows the possibility and feasibility ofimplementing the proposed RFID on ASIC to enhance backscatter signalstrength. ASIC's NMOS/PMOS transistors with unbalanced on-stateimpedances can lead to larger RCS and thus increase the backscattersignal. In order to design ASIC that can effectively enhance thebackscatter signal, first we need to understand the impedance model ofthe proposed RFID tag. Output impedance of a power supply network inintegrated circuits is the parallel combination of output impedances ofindividual power-supply connections of all flip-flops [15]. The moreflip-flops are connected, the more individual power supplies areconnected in parallel, which reduces impedance. That is, the total inputimpedance of the proposed RFID tag is inversely related to the logicutilization N. Given this relationship between logic utilization andinput impedance, we introduce a modulation loss factor, M, which relatesthe total tag's modulation loss to transistors' impedance variation. Mcan be expressed as,

M(x %)=¼|((R1(x %)−377*)÷(R1(x %)+377))−((R0(x %)−377*)÷(R0(x%)+377))|²   (1)

where R1(x %) and R0(x %) are the estimated high state (1s) resistanceand low state (0s) resistance of the FPGA chip. Parameter x representsthe percentage of total logic resources being configured. R1(x %) andR0(x %) are defined as,

R1(x %)=(R1(10%)÷(x %÷10%))+Rpkg  (2) and

R0(x %)=(R0(10%)÷(x %÷10%))+Rpkg  (3)

R1(10%) and R0(10%) are the estimated high state (1s) and low state (0s)resistances of an FPGA chip where 10% of total resources are utilized.Rpkg is the estimated resistance contributed by the package of the ICchip, e.g., wire bonds inside the chip case. The input impedance of thetag is equal to free space impedance, 377Ω, since there is no antennabut only air at the interface between the carrier signal and FPGA chip.Note that total impedance may also be affected by GPIO pins. For all theRFID designs proposed in this paper, we disconnect the traces thatconnect the chip and GPIO pins, and thus, GPIO pins do not affect theimpedance variation created by the switching transistors. As a result,the proposed impedance model in (1) does not include the influence fromGPIO pins. According to reference [27], typical values of R0 and R1 arein kΩ range and the values of R0 and R1 are inversely proportional tothe W/L ratio of the device (ratio of width and length). Therefore, bytuning transistor's W/L ratio, one can control the values of R0 and R1,modulation loss factor M, and the corresponding backscatter power. Inorder to estimate R0(10%), and R1(10%), this disclosure first configuresthe FPGA 499 of FIG. 4 with a carrier wave frequency of 17.46 GHz,modulating frequency fm=900 kHz and logic utilization varying from 10%to 100% In one non-limiting example of this disclosure, the experimentmeasures the corresponding backscattered power at 17.46 GHz+900 kHz.Next steps include performing curve fitting to estimate the optimalvalue of (R0(10%), R1(10%)) as (18.8 kΩ, 20.4 kΩ), which is withinreasonable range as noted in Reference [27].

The estimated value of Rpkg is found to be in the range of several ohmsbased on the dimensions of the wire bonds provided by [32] and theformulae in reference [33]. It is found that Rpkg has very minor impactto the total resistance since Rpkg is in the range of several ohms whileR0 and R1 are in the kilo-ohm range. Next, by using (1), one canestimate the value of M for the FPGA processor as −39.1 dB. We havedesigned an ASIC with (R0, R1)=(6 kΩ, 100 kΩ), and M=−9.1 dB. Comparisonof modulation loss factor M between the current FPGA processor and theproposed ASIC design is summarized in Table I. Accordingly, one canobserve that by increasing the difference between ASICs' two impedancestates R0 and R1, modulation loss factor M and the backscatter power canbe effectively enhanced by 30 dB. Next, this disclosure includes resultsof conducted simulation of MOSFET transistors with Keysight AdvancedDesign System to demonstrate that the proposed ASIC design in Table Ican be achieved by tuning transistors' W/L ratios. Schematic design ofthe simulation is presented in FIG. 9. BSIM4 NMOS 900 and PMOS 915transistor models similar to those of references [34], [35] are based on0.16 um process, i.e., the minimum length of gate (L) of a transistor is0.16 um. FIGS. 10 and 11 present the simulation results of the R0 ofNMOS transistor 900 and R1 of PMOS transistor 915 with different W/Lratios as the drain voltage (VDD) sweeps from 0 V to 3 V. Results showthat the proposed ASIC design (third row in Table I) with (R0, R1)=(6kΩ, 100 kΩ) can be achieved by using (W/L)NMOS=3, (W/L)PMOS=1, andVDD=1.5 V.

TABLE 1 COMPARISON OF MODULATION LOSS FACTOR (M) (R0, R1) LogicEnhancement Designs (kΩ) Utilization M of M Current FPGA (18.8, 20.4)100% −39.1 dB +0 dB ASIC  (6, 100) 100% −9.1 dB +30 dB

An Agilent MXG N5183A Signal Generator with input power of 15 dBm (31.6mW) is used as a signal source and an Agilent MXA N9020A Vector SignalAnalyzer is used to record the signals. An Altera DEO-Cyclone V FPGAboard 1200 is used as the RFID tag as shown in FIG. 12A. Forinterrogation, this non-limiting example uses double ridge horn antennas1210A, 1210B (Com-Power AH-118) shown in FIG. 12B for 5.8 GHzmeasurements. Double ridge horn antenna operates from 0.7 GHz to 18 GHzwith average isotropic gain of 10 dBi. FIG. 12C shows measurement setupwith WR-62 standard gain horn antennas 1220A, 1220B (PE9854/SF-20) thatoperate from 12.4 GHz to 18 GHz with average isotropic gain of 20 dBi.Finally, FIG. 12D shows measurement setup with horn antennas 1230A,1230B (A-INFO LB-28-10) operating from 26.5 GHz to 40 GHz with averageisotropic gain of 10 dBi. Note that in FIGS. 12B and 12C, a 3-mm thickplastic case 1205 is placed between the Tx/Rx and the FPGA board 1200 todemonstrate that the proposed RFID tag can be potentially integratedinto electronic devices with plastic enclosures, e.g., laptops,smartphones, tablets, etc. Note that the experiments show use ofdifferent horn antennas because none of them cover all frequencies ofinterest, i.e., 5.8 GHz, 17.46 GHz, and 26.5 GHz.

This disclosure also illustrates investigations directed to the optimalcarrier frequency (f_(carrier)) to interrogate the proposed RFID tag andthe maximum distance at which the signal can be received. Themeasurement setup in FIG. 12G has a transmission power Pt=15 dBm andmodulation frequency fm=900 kHz. After sweeping carrier frequencies from1 GHz to 18 GHz, researchers have found that the highest SNR is around40 dB in the frequency range between 17 and 18 GHz. To test how far awaya reader can receive backscattered signal, this disclosure shows resultsthat configured a 1 bit RFID with 100% logic utilization in order tomaximize the SNR and to achieve longer distance. The FPGA board wasplaced at 2 m away from the carrier wave transmitter Tx andinterrogation receiver Rx. The fcarrier is set at 17.46 GHz with Pt=15dBm and fm=900 kHz. FIG. 13 shows the measured backscatter signal at adistance of 2 m. It is observed that the sideband 1305 appears atfcarrier+900 kHz with SNR around 5 dB. Empirically, experiments havedetermined that a minimum 2.7% of total logic resources is needed toprovide one observable sideband (bit) with SNR around 3 dB atTx/Rx-to-tag distance=20 cm. This implies that an FPGA chip can be usedfor multiple tasks, i.e., enable RFID tag without interrupting normalfunction of the FPGA chip. For example, if an FPGA is configured forintense data processing, designers can reduce the number of bits andlogic utilization of each bit, e.g., an 1-bit RFID allocated with 8% oftotal logic resources, leaving 92% of free logic resources for dataprocessing; if an FPGA chip is mainly idle, designers can increase thenumber of bits and logic utilization of each bit, e.g., an 8-bit RFIDwith each bit assigned with 10% of total logic resources for higher SNRand data rate, leaving 20% of free logic resources for non-RFIDactivities, e.g., computing, DSP, etc. Therefore, there is great designflexibility while still supporting normal functionality of an FPGA-basedsystem. Regarding power consumption, given an Altera Cyclone V FPGAconfigured at 100% logic utilization, a typical DC current consumptionis 8.1 mA with a supply voltage of 1.1 V, which leads to a maximum powerconsumption of 9.5 dBm (8.91 mW) [36].

This disclosure further illustrates how the proposed RFID tag can beused for several different applications: 1) static IDs with 6, 12, and36 bits; 2) dynamic multi-bit communications; 3) high data ratecommunications. The first application is static ID with 6 bits (FIGS. 14and 16), 12 bits (FIGS. 15 and 17), and 36 bits (FIG. 18), respectively.The “static” term means that the designed bit pattern does not changeover time, such as illustrated earlier in FIG. 3. Information stored onthe tag depends on total number of bits. This disclosure shows thatmultiple shift registers designed as described in FIG. 7 configuremulti-bit RFID design. For the 6-bit, 12-bit, and 36-bit RFIDs, fm isset in a range of 860 kHz-1.04 MHz (FIG. 14), 700 kHz-1.04 MHz (FIG.15), and 300 kHz-1.04 MHz (FIG. 18) and 15%, 8.3%, and 2.7% of logicresources are assigned to each bit, which contributes a total logicutilization of 90%, 99.7%, and 97.2% and a corresponding powerconsumption of 9.04 dBm (8.02 mW), 9.49 dBm (8.88 mW), and 9.38 dBm(8.66 mW), respectively. Each bit can be turned on and off individuallyto generate binary signals is and 0s with up to 68.7 billion (2³⁶)combinations of unique IDs. The results demonstrate 6 bits and 12 bitsstatic IDs at both 5.8 GHz and 26.5 GHz. The more bits are configured,the less logic resources are assigned to each bit, which requires higherantenna gain to accommodate lower SNR. As a result, experiments of thisdisclosure were able to observe signals for a 36 bits static ID (FIG.18) only at 17.46 GHz because it had the highest SNR. Measurementresults are shown in FIGS. 14-18.

One should note that the sideband power levels, e.g., 1400, 1500, 16,00,1700, 1800 show respective bit transmission (1-6; 1-12; 1-36) atrespective modulating frequencies within each range shown in FIGS.14-18. It can be observed that all bits are clearly identified andseparated at least 15 kHz apart with SNRs ranging from 6 dB to 20 dB,providing sufficient margins for signal detection. These example designsare not limiting of the disclosure but do demonstrate flexible carrierfrequency selection and bits configuration. Note that in FIG. 18, due toattenuation, harmonics of lower sidebands do not cause observableinterference to the higher sidebands. For the measurement setup, Pt is15 dBm, Tx/Rx-tag distance is 20 cm. Note that the plastic enclosure asobstruction between the tag and the Tx/Rx can cause extra 1 to 2 dBattenuation. The measurement results shown in FIGS. 14-18 are withoutobstruction for better SNR demonstration.

The second application is dynamic multi-bit communications. The“dynamic” term means the designed bit pattern changes over time.Compared to the static IDs discussed above here individual bit is turnedon and off over time at a switching frequency (fs) to transmitinformation as shown in FIGS. 19-21. As a result, information stored onthe tag is not limited by total number of bits but depends on fs andtotal transmitting time. We design 4-bit, 8-bit, and 12-bit RFID tags totransmit specific symbols and successfully detect the symbols at thereceiver. Each bit is allocated with 8% of logic resources and fs is setat 100 Hz. Consequently, the 4, 8, and 12 bits designs have a totallogic utilization of 32%, 64%, and 96%, a corresponding data rate of 400bits/sec, 800 bits/sec, and 1.2 kbits/sec, and a corresponding powerconsumption of 4.55 dBm (2.85 mW), 7.56 dBm (5.7 mW), and 9.32 dBm (8.55mW), respectively. FIG. 19 presents symbol patterns measured at thereceiver for the 4 bits design. Data symbols are designed in thefollowing patterns: (1111), (1000), (1010), (0101), (0011), (0111). Thefm ranges from 1 MHz to 1.14 MHz to accommodate all 4 bits. Measurementresults show that all the symbols are successfully detected and matchthe designed signal patterns. In the 8 bits (FIG. 20) and 12 bits (FIG.21) designs, the fm ranges from 1 MHz to 1.39 MHz and from 1 MHz to 1.79MHz, respectively. The 8 bits design has symbol patterns of (11111111),(00000000), (10011100), (10000011) and the 12 bits design has symbolpatterns of (111111111111), (000000000000), (100000011100),(100000000011). Similarly, all symbols of the 8 bits and 12 bits RFIDare successfully detected as shown in FIGS. 20 and 21. For themeasurement setup, Pt is 15 dBm, Tx/Rx-tag distance is 20 cm,interrogation frequency is 17.46 GHz. Note that the plastic enclosure asobstruction between the tag and the Tx/Rx can cause extra 1 to 2 dBattenuation. The measurement results shown in FIGS. 1 C. DynamicSingle-Bit Communications With Maximum Data Rate.

The third application is focused on providing high data ratecommunication between the interrogator and the tag. In one non-limitingset-up, experimental designs have a 1-bit RFID with 100% logicutilization and maximum power consumption of 9.5 dBm (8.91 mW) tomaximize SNR. The fm is set at 1.92 MHz and the fs is set at 100 kHz,providing a data rate of 100 kbits/sec. In order to estimate the biterror rate (BER), this embodiment uses the VSA with a sampling rate of2.56 MHz to record more than 1 million transmitting bits (1091227 bits)for around 11 seconds. The RFID tag modulates the carrier signals with atesting symbol pattern of (111010). FIG. 22 presents the measured signalstrength of the transmitted symbols. Solid curve is the modulatedbackscatter signals measured by the VSA, while red circles arepost-measurement signal processing sampled signals. In order to detectbit 0 and bit 1, a threshold value of −81 dBm is chosen since itprovides the lowest BER. Our signal processing results show that only 2errors are detected among all 1091227 transmitted bits, that is, aproposed RFID tag achieves a BER of 0.00000183 (10-6) at a data rate of100 kbits/sec. For the measurement setup, Pt is 15 dBm, Tx/Rx-tagdistance is 20 cm, interrogation frequency is 17.46 GHz. Note that theplastic enclosure as obstruction between the tag and the Tx/Rx can causeextra 1 to 2 dB attenuation. The measurement results shown in FIG. 22are without obstruction for better SNR demonstration.

FIG. 23 illustrates an exemplary computer that may comprise all or aportion of an antenna-less RFID device or antenna-less RFID controlsystem. Conversely, any portion or portions of the computer illustratedin FIG. 23 may comprise all or an antenna-less RFID device orantenna-less RFID control system. As used herein, “computer” may includea plurality of computers. The computers may include one or more hardwarecomponents such as, for example, a processor 1021, a random-accessmemory (RAM) module 1022, a read-only memory (ROM) module 1023, astorage 1024, a database 1025, one or more input/output (I/O) devices1026, and an interface 1027. Alternatively, and/or additionally, thecomputer may include one or more software components such as, forexample, a computer-readable medium including computer executableinstructions for performing a method associated with the exemplaryembodiments such as, for example, an algorithm for transmitting a 36-bitstatic ID. It is contemplated that one or more of the hardwarecomponents listed above may be implemented using software. For example,storage 1024 may include a software partition associated with one ormore other hardware components. It is understood that the componentslisted above are exemplary only and not intended to be limiting.

Processor 1021 may include one or more processors, each configured toexecute instructions and process data to perform one or more functionsassociated with a computer for controlling a system (e.g., configuringthe switching devices) and/or receiving and/or processing and/ortransmitting data associated with a network of antenna-less RFIDdevices. Processor 1021 may be communicatively coupled to RAM 1022, ROM1023, storage 1024, database 1025, I/O devices 1026, and interface 1027.Processor 1021 may be configured to execute sequences of computerprogram instructions to perform various processes. The computer programinstructions may be loaded into RAM 1022 for execution by processor1021. RAM 1022 and ROM 1023 may each include one or more devices forstoring information associated with operation of processor 1021. Forexample, ROM 1023 may include a memory device configured to access andstore information associated with the computer, including informationfor identifying, initializing, and monitoring the operation of one ormore components and subsystems. RAM 1022 may include a memory device forstoring data associated with one or more operations of processor 1021.For example, ROM 1023 may load instructions into RAM 1022 for executionby processor 1021.

Storage 1024 may include any type of mass storage device configured tostore information that processor 1021 may need to perform processesconsistent with the disclosed embodiments. For example, storage 1024 mayinclude one or more magnetic and/or optical disk devices, such as harddrives, CD-ROMs, DVD-ROMs, or any other type of mass media device.

Database 1025 may include one or more software and/or hardwarecomponents that cooperate to store, organize, sort, filter, and/orarrange data used by the computer and/or processor 1021. For example,database 1025 may store data related to the remote sensing datacorrelated with signal attenuation. The database may also contain dataand instructions associated with computer-executable instructions forcontrolling a system (e.g., a remote sensing and modeling system) and/orreceiving and/or processing and/or transmitting data associated with anetwork of sensor nodes used to measure water quality. It iscontemplated that database 1025 may store additional and/or differentinformation than that listed above.

I/O devices 1026 may include one or more components configured tocommunicate information with a user associated with computer. Forexample, I/O devices may include a console with an integrated keyboardand mouse to allow a user to maintain a database of digital images,results of the analysis of the digital images, metrics, and the like.I/O devices 1026 may also include a display including a graphical userinterface (GUI) for outputting information on a monitor. I/O devices1026 may also include peripheral devices such as, for example, aprinter, a user-accessible disk drive (e.g., a USB port, a floppy,CD-ROM, or DVD-ROM drive, etc.) to allow a user to input data stored ona portable media device, a microphone, a speaker system, or any othersuitable type of interface device.

Interface 1027 may include one or more components configured to transmitand receive data via a communication network, such as the Internet, alocal area network, a workstation peer-to-peer network, a direct linknetwork, a wireless network, or any other suitable communicationplatform. For example, interface 1027 may include one or moremodulators, demodulators, multiplexers, demultiplexers, networkcommunication devices, wireless devices, antennas, modems, radios,receivers, transmitters, transceivers, and any other type of deviceconfigured to enable data communication via a wired or wirelesscommunication network.

Considering the numerous configurations for the computerized equipmentdescribed above, this disclosure incorporates embodiments of varyingscope that implements the concepts discussed herein. Broadly, in onenon-limiting embodiment,

A semi-passive radio frequency identification (RFID) tag may becharacterized as a digital circuit 300, 499 comprising switchingcomponents 305, 315, 325, 400, 405, 410, 415 operating within aninterrogation range of an incident carrier wave 115. A plurality ofinput connections 174 and output connections 175 directing datacommunications (D) through the switching components within the digitalcircuit, wherein the data communications are subject to switchingoperations of the switching components between at least one of the inputconnections 174, D and at least one of the output connections 175, Q. Abackscatter response 287A, 287B is reflected from the digital circuitupon arrival of the incident carrier wave, wherein the backscatterresponse is a modulated backscatter response 727 in the presence of theswitching operations. The digital circuit 300, 499 implements thebackscatter response 287A, 287B in the absence of an analog elementoperating as a separate antenna structure. Information channels 729 ofmodulated backscatter data 727 are discernible from the backscatterresponse 287A, 287B by associated computerized equipment such as varioustransceiver embodiments. Respective switching clocks 302 are programmedto exhibit a modulation frequency for each corresponding set of theswitching components. Respective sections of the digital circuitmodulate the backscatter response at a respective one of the modulationfrequencies. A static identification code is discernible from theinformation channels of modulated backscatter data. The digital circuitincludes a field programmable gate array. The digital circuit includesat least one application specific integrated circuit (ASIC). The digitalcircuit includes at least one processor that controls the switchingcomponents according to a software program stored in an associatedmemory that is in data communication with the processor, and theprocessor activities implemented by the software program control thebackscatter response according to instructions from the softwareprogram. In other embodiments, the digital circuit may include an array499 of serially connected switching components, 400A-400D, 405A-405D,410A-415D, 420A-420D, and the array includes parallel operated groups ofthe serially connected switching components. The parallel operatedgroups switch at different modulation frequencies.

In other non-limiting embodiments, a semi-passive radio frequencyidentification (RFID) tag may be described as a digital circuit having aclock connected to switching components having a plurality of respectiveoutputs switched by a clock input, wherein the clock input has a clockfrequency f_(clock) and the respective outputs exhibit a modulatingfrequency f_(m). Respective output impedances for the switchingcomponents care configured for updating in response to the clock input,and a respective radar cross section response is exhibited at each ofthe switching components. The updated output impedances modulate therespective radar cross sections, and respective information channels ofdata are discernible from modulations of the respective radar crosssection responses. The respective output impedances correspond torespectively switched states of RF loads at each of the switchingcomponents, wherein the states vary the tag's reflection coefficient. Atleast a static identification code or even a dynamically updated code isdiscernible from the information channels of data. The semi-passive RFIDtag may include a digital circuit having an array of the switchingcomponents arranged in serial connection as a linear feedback shiftregister, wherein an output of a last switching component in the serialconnection is connected as an input to a first switching component inthe serial connection. The data is repeated across an active switchingperiod and static across a quiet period within the modulating frequency.The modulations of respective radar cross sections are configured tomodulate an input carrier wave having a carrier frequency of f_(carrier)and directed to the digital circuit in a wireless transmission, and themodulated carrier wave is discernible in a respective informationchannel comprising a modulated backscatter signal having a firstharmonic located at f_(carrier)+/−f_(m). In another non-limitingembodiment, the semi-passive RFID tag utilizes a highest frequency forsidebands of the modulated backscatter signal, relative to the carrierfrequency, that is less than two times the lowest frequency for detectedsidebands. The semi-passive RFID tag in the form of digital circuit maybe formed in an application specific integrated circuit (ASIC). Thedigital circuit includes an array of serially connected switchingcomponents, and the array includes parallel operated groups of theserially connected switching components, and the parallel operatedgroups switch at different modulation frequencies.

Another disclosed embodiment includes a semi-passive radio frequencyidentification (RFID) tag having an application specific integratedcircuit (ASIC) with a plurality of logical switching elements having aclock connected to respective NMOS and PMOS transistors having aplurality of respective outputs switched by a clock input, wherein theclock input has a clock frequency fclock and the respective outputsexhibit a modulating frequency f_(m). Respective input impedances andoutput impedances for the transistors are configured for updating inresponse to switching activity in accordance with the clock input,wherein the transistors comprise unbalanced on-state impedances. Arespective radar cross section response is exhibited at the switchingcomponents, wherein updated output impedances modulate the respectiveradar cross section responses. Respective information channels of dataare discernible from modulations of the respective radar cross sectionresponses. In some embodiments, the transistors are connected in anarray comprising respective parallel power sources in electricalcommunication with groups of serially connected transistors, and whereinthe array has a logic utilization factor N that represents a totalnumber of groups of serially connected transistors. The semi-passiveradio frequency identification (RFID) tag may have a total inputimpedance of the RFID tag that is inversely related to the logicutilization factor N. The semi-passive radio frequency identification(RFID) tag may be a N value that is greater than 2.7 percent. Thesemi-passive radio frequency identification (RFID) tag exhibitsinformation channels that are configured for interrogation with acarrier wave signal that has a frequency selected from 5.8 GHz, 17.46GHz, and 26.5 GHz.

In a system for using backscatter data channels from an RFID tag adigital circuit includes a clock connected to switching componentshaving a plurality of respective outputs switched by a clock input,wherein the clock input has a clock frequency fclock and the respectiveoutputs exhibit a modulating frequency f_(m). Respective outputimpedances for the switching components are configured for updating inresponse to the clock input. A respective radar cross section responseexhibited at the switching components, wherein updated output impedancesmodulate the respective radar cross sections. Respective informationchannels of data discernible from modulations of the respective radarcross section responses, and an interrogating device includes atransceiver directing a carrier wave to the digital circuit andreceiving backscatter signals from the digital circuit, wherein thebackscatter signals are related to the respective radar cross sectionresponses, and wherein the transceiver detects the data from thebackscatter signals. In one system for using backscatter data channelsfrom an RFID tag, the carrier wave has a frequency selected from 5.8GHz, 17.46 GHz, and 26.5 GHz. A system for using backscatter datachannels from an RFID tag operates with the respective output impedancescorresponding to respectively switched states of RF loads at each of theswitching components, wherein the states vary the tag's reflectioncoefficient. The digital circuit comprises an array of logical switchingelements configured to transmit the data in respective bits ofinformation. Each respective bit is separately switched in a bitpattern. In some embodiments, the bit pattern changes over time toexhibit a dynamic bit pattern. A system for using backscatter datachannels from an RFID tag may include the bit pattern having individualbits that are turned on and off over time at a switching frequency (fs)to transmit the data. A system for using backscatter data channels froman RFID tag may include one of a single bit pattern, a 4-bit pattern, an8-bit pattern, and a 12-bit pattern.

The figures illustrate the architecture, functionality, and operation ofpossible implementations of systems, methods and computer programproducts according to various implementations of the present invention.In this regard, each block of a flowchart or block diagrams mayrepresent a module, segment, or portion of code, which comprises one ormore executable instructions for implementing the specified logicalfunction(s). It should also be noted that, in some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts, or combinations of special purpose hardware andcomputer instructions.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theimplementation was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious implementations with various modifications as are suited to theparticular use contemplated.

Any combination of one or more computer readable medium(s) may be usedto implement the systems and methods described hereinabove. The computerreadable medium may be a computer readable signal medium or a computerreadable storage medium. A computer readable storage medium may be, forexample, but not limited to, an electronic, magnetic, optical,electromagnetic, infrared, or semiconductor system, apparatus, ordevice, or any suitable combination of the foregoing. More specificexamples (a non-exhaustive list) of the computer readable storage mediumwould include the following: an electrical connection having one or morewires, a portable computer diskette, a hard disk, a random access memory(RAM), a read-only memory (ROM), an erasable programmable read-onlymemory (EPROM or Flash memory), an optical fiber, a portable compactdisc read-only memory (CD-ROM), an optical storage device, a magneticstorage device, or any suitable combination of the foregoing. In thecontext of this document, a computer readable storage medium may be anytangible medium that can contain, or store a program for use by or inconnection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing.

Computer program code for carrying out operations for aspects of thepresent invention may be written in any combination of one or moreprogramming languages, including an object-oriented programming languagesuch as Java, Smalltalk, C++ or the like and conventional proceduralprogramming languages, such as the “C” programming language or similarprogramming languages. The program code may execute entirely on theuser's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

While the methods and systems have been described in connection withpreferred embodiments and specific examples, it is not intended that thescope be limited to the particular embodiments set forth, as theembodiments herein are intended in all respects to be illustrativerather than restrictive.

Unless otherwise expressly stated, it is in no way intended that anymethod set forth herein be construed as requiring that its steps beperformed in a specific order. Accordingly, where a method claim doesnot actually recite an order to be followed by its steps or it is nototherwise specifically stated in the claims or descriptions that thesteps are to be limited to a specific order, it is no way intended thatan order be inferred, in any respect. This holds for any possiblenon-express basis for interpretation, including: matters of logic withrespect to arrangement of steps or operational flow; plain meaningderived from grammatical organization or punctuation; the number or typeof embodiments described in the specification.

Overall, in one non-limiting theory of operation, existing analog-signalside-channels, such as electromagnetic emanations 120 shown in prior artFIG. 1, are a consequence of current-flow changes that are dependent onactivity inside electronic circuits. This disclosure introduces a newclass of side-channels that is a consequence of impedance changes inswitching circuits, and are referred to as an impedance-basedside-channel. One example of such a side-channel is when digital logicactivity causes incoming electromagnetic signals of carrier waves, suchas continuous wave 115 from a reader 110, to be modulated as they arereflected (backscattered), at frequencies that depend on both theincoming EM signal and the circuit activity. This can cause EMinterference or leakage of sensitive information, but it can also beleveraged for radio frequency identification (RFID) tag design. Thisdisclosure first introduces a new class of side-channels that, accordingto one non-limiting theory, is a consequence of impedance differences inswitching circuits, referred to as an impedance-based side-channel.Having demonstrated that the impedance difference between transistorgates in the high-state and in the low-state changes the radar crosssection (RCS) of a digital circuit and modulates the backscatteredsignal, this disclosure sets forth results of experiments that haveinvestigated the possibility of implementing the proposed RFID on ASICfor signal enhancement. Accordingly, a digital circuit can be used as asemi-passive RFID tag. To illustrate the adaptability of the proposedRFID, this disclosure shows a variety of RFID applications acrosscarrier frequencies at 5.8 GHz, 17.46 GHz, and 26.5 GHz to demonstratethe flexible carrier frequency selection and bit configuration.

These applications demonstrate flexible carrier frequency selection andbits configuration, such as static IDs with 6, 12, and 36 bits, whichprovide up to 68.7 billion (2³⁶) combinations of unique IDs, andmulti-bit (4, 8, and 12 bits) dynamic RFIDs. A maximum data rate of 100kbits/sec with a bit error rate (BER) of 0.00000183 (10-6) is achieved.

Throughout this application, various publications may be referenced. Thedisclosures of these publications in their entireties are herebyincorporated by reference into this application in order to more fullydescribe the state of the art to which the methods and systems pertain.

It will be apparent to those skilled in the art that variousmodifications and variations can be made without departing from thescope or spirit. Other embodiments will be apparent to those skilled inthe art from consideration of the specification and practice disclosedherein. It is intended that the specification and examples be consideredas exemplary only, with a true scope and spirit being indicated byclaims herein.

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1. A semi-passive radio frequency identification (RFID) tag comprising:a digital circuit comprising switching components operating within aninterrogation range of an incident carrier wave; a plurality of inputconnections and output connections directing data communications throughthe switching components within the digital circuit, wherein the datacommunications are subject to switching operations of the switchingcomponents between at least one of the input connections and at leastone of the output connections; and a backscatter response reflected fromthe digital circuit upon arrival of the incident carrier wave, whereinthe backscatter response is a modulated backscatter response in thepresence of the switching operations.
 2. The RFID tag of claim 1,wherein the digital circuit implements the backscatter response in theabsence of an analog element operating as a separate antenna structure.3. The RFID tag of claim 1, further comprising information channels ofmodulated backscatter data discernible from the backscatter response. 4.The RFID tag of claim 3, wherein the respective switching clocks areprogrammed to exhibit a modulation frequency for each corresponding setof the switching components.
 5. The RFID tag of claim 4, wherein therespective sections of the digital circuit modulate the backscatterresponse at a respective one of the modulation frequencies.
 6. The RFIDtag claim 5, comprising a static identification code discernible fromthe information channels of modulated backscatter data.
 7. The RFID tagof claim 1, wherein said digital circuit comprises a field programmablegate array.
 8. The RFID tag of claim 1, wherein said digital circuitcomprises at least one application specific integrated circuit (ASIC).9. The RFID tag of claim 1, wherein said digital circuit comprises atleast one processor that controls the switching components according toa software program stored in an associated memory that is in datacommunication with the processor, wherein processor activitiesimplemented by the software program control the backscatter responseaccording to instructions from the software program.
 10. The RFID tag ofclaim 1, wherein said digital circuit comprises an array of seriallyconnected switching components, and said array comprises paralleloperated groups of said serially connected switching components, andsaid parallel operated groups switch at different modulationfrequencies.
 11. A semi-passive radio frequency identification (RFID)tag comprising: a digital circuit comprising a clock connected toswitching components having a plurality of respective outputs switchedby a clock input, wherein the clock input has a clock frequencyf_(clock) and the respective outputs exhibit a modulating frequencyf_(m); respective output impedances for the switching componentsconfigured for updating in response to the clock input; a respectiveradar cross section response exhibited at each of the switchingcomponents, wherein updated output impedances modulate the respectiveradar cross sections; respective information channels of datadiscernible from modulations of the respective radar cross sectionresponses.
 12. The semi-passive RFID tag according to claim 11, whereinthe respective output impedances correspond to respectively switchedstates of RF loads at each of the switching components, wherein thestates vary the tag's reflection coefficient.
 13. The semi-passive RFIDtag according to claim 11, wherein the modulations of respective radarcross sections are configured to modulate an input carrier wave having acarrier frequency of f_(carrier) and directed to the digital circuit ina wireless transmission, and wherein the modulated carrier wave isdiscernible in a respective information channel comprising a modulatedbackscatter signal having a first harmonic located atf_(carrier)+/−f_(m).
 14. The semi-passive RFID tag according to claim11, wherein said digital circuit is formed in an application specificintegrated circuit (ASIC).
 15. The semi-passive RFID tag according toclaim 11, wherein said digital circuit comprises an array of seriallyconnected switching components, and said array comprises paralleloperated groups of said serially connected switching components, andsaid parallel operated groups switch at different modulationfrequencies.
 16. A system for using backscatter data channels from anRFID tag, comprising: a digital circuit comprising a clock connected toswitching components having a plurality of respective outputs switchedby a clock input, wherein the clock input has a clock frequencyf_(clock) and the respective outputs exhibit a modulating frequencyf_(m); respective output impedances for the switching componentsconfigured for updating in response to the clock input; a respectiveradar cross section response exhibited at the switching components,wherein updated output impedances modulate the respective radar crosssections; respective information channels of data discernible frommodulations of the respective radar cross section responses; and aninterrogating device comprising a transceiver directing a carrier waveto the digital circuit and receiving backscatter signals from thedigital circuit, wherein the backscatter signals are related to therespective radar cross section responses, and wherein the transceiverdetects the data from the backscatter signals.
 17. A system for usingbackscatter data channels from an RFID tag according to claim 16,wherein the respective output impedances correspond to respectivelyswitched states of RF loads at each of the switching components, whereinthe states vary the tag's reflection coefficient.
 18. A system for usingbackscatter data channels from an RFID tag according to claim 17,wherein the digital circuit comprises an array of logical switchingelements configured to transmit the data in respective bits ofinformation.
 19. A system for using backscatter data channels from anRFID tag according to claim 18, wherein each respective bit isseparately switched in a bit pattern.
 20. A system for using backscatterdata channels from an RFID tag according to claim 19, wherein the bitpattern changes over time to exhibit a dynamic bit pattern.